1. Field of the Invention
The embodiments of the invention generally relate to performance screening of digital integrated circuits and, more particularly, to a circuit structure and method for selectively operating a digital integrated circuit, such as a memory device, in either a functional mode or in a performance screening mode.
2. Description of the Related Art
Variation aware timing (VAT) methodologies were developed to provide customers with a timing tool that properly takes into account across-chip parameter variations (e.g., channel length, threshold voltage (Vt), etc.) that impact timing. Performance screen ring oscillators (PSRO) are often used in VAT analyses of integrated circuits (e.g., of application-specific integrated circuits (ASICs)). These PSROs are on-chip structures comprising a ring of free-running, series-connected devices that oscillates at a frequency. At an output node, the oscillation frequency is measured and provides a relative indication of the actual speed of the integrated circuit under test in order to determine whether the integrated circuit meets performance specifications. Unfortunately, PSROs do not typically incorporate logic structures that dominate digital integrated circuits, such as memory devices (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc). Thus, conventional PSROs do not effectively track digital integrated circuit performance and, more particularly, do not effectively track memory performance. This failure to effectively track performance inevitably results in significant yield loss (e.g., due to overly-conservative and less-competitive timing models). Furthermore, as the size of memory arrays increases, the discrepancy between PSRO performance and memory array performance grows larger. Therefore, there is a need in the art for a more effective circuit structure and method for screening performance in digital integrated circuits and, more particularly, in memories.